SC417/SC427
29
PCB Layout Guidelines
The optimum layout for the SC417/SC427 is shown in
Figure 15. This layout shows an integrated FET buck regu-
lator with a maximum current of 10A. The total PCB area is
approximately 20 x 25 mm.
Critical Layout Guidelines
The following critical layout guidelines must be followed
to ensure proper performance of the device.
IC Decoupling capacitors
PGND plane
AGND island
FB, VOUT, and other analog control signals
BST, ILIM, and LX
CIN and COUT placement and Current Loops
IC Decoupling Capacitors
A 0.1 糉 capacitor must be located as close as
possible to the IC and directly connected to pins
3 (V5V) and 4 (AGND).
All other decoupling capacitors must be located
as close as possible to the IC.
"
"
"
"
"
"
"
"
PGND Plane
PGND requires its own copper plane with no
other signal traces routed on it.
Copper planes, multiple vias and wide traces are
needed to connect PGND to input capacitors,
output capacitors, and the PGND pins on the IC.
The PGND copper area between the input
capacitors, output capacitors and PGND pins
must be as tight and compact as possible to
reduce the area of the PCB that is exposed to
noise due to current flow on this node.
Connect PGND to AGND with a short trace or
0& resistor. This connection should be as close
to the IC as possible.
AGND Island
AGND should have its own island of copper with
no other signal traces routed on this layer that
connects the AGND pins and pad of the IC to the
analog control components.
All of the components for the analog control cir-
cuitry should be located so that the connections
"
"
"
"
"
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Applications Information (continued)
VOUT Plane
on Top layer
L
CLDO
C
IN
CFF
RFB2
RFB1
RILIM
RLDO2
RLDO1
LX plane on inner
or bottom layer
All components
shown Top Side
AGND plane on
inner layer
V
IN
plane on inner
or bottom layer
RGND AGND connects to
PGND close to SC417/SC427
Pin 1 marking
SC417/SC427
with vias for LX,
AGND, VIN
C
OUT
PGND on inner
or bottom layer
PGND
PGND on
Top Layer
V5V Decoupling Capacitor
Figure 15 PCB Layout
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